Geo Part : A System Partitioning Algorithm to Maximize Sleep Time

Sleep mode and exploiting it to maximize sleep time are of great importance in low power synthesis of digital circuits. The motivation is to de-activate the memory refresh circuitry, apply power down or just disable the clock signals during the inactive periods of operation of circuit elements, and thus minimize the power consumption. Since it is impractical to have a separate set of control signals for each circuit element (otherwise, the control itself would consume a lot of power), it is advisable to partition a circuit based on the activity patterns of its elements so that the partitions can be switched into sleep mode for long periods of time. A partition can be switched into sleep mode during time interval I if all elements in that partition are idle during I . In this paper, we present a heuristic algorithm for this problem. Due to the geometric avor of this problem, the classical graph-based partitioning schemes cannot be applied directly. In this paper we present Geo Part , a geometric partitioning heuristic based on the iterative improvement techniques, for this problem. An e cient implementation of Geo Part using segment tree data structure is described. Design of accompanying sleep mode controller and the associated hardware issues are discussed. Experiments for memory segmentation for low power synthesis of application-speci c integrated circuits were conducted on a number of sorting, matrix multiplication, and DSP algorithms to show the e ectiveness of our approach. The percentage of saving in the power consumption due to memory on the tested data ranged from 3% to 60%, with an average savings of 20.02%. Directions for further research in this area are presented.